Liquid crystal display device and fabricating method thereof

ABSTRACT

A liquid crystal display device, including: first and second substrates; a gate line on the first substrate; a data line crossing the gate line having a gate insulating film therebetween to define a pixel area; a pixel electrode formed of a transparent conductive film in a pixel hole passing through the gate insulating film in the pixel area; and a thin film transistor including a gate electrode, a source electrode, a drain electrode, and a semiconductor layer defining a channel between the source electrode and the drain electrode, wherein the semiconductor layer overlaps with a source and drain metal pattern including the data line, the source electrode and the drain electrode; and wherein the drain electrode protrudes from the semiconductor layer toward inside of the pixel electrode to be connected to the pixel electrode.

This application claims the benefit of Korean Patent Application No.P2004-118600 filed in Korea on Dec. 31, 2004, which is herebyincorporated by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to a thin film transistor substrate applied to adisplay device, and more particularly to a thin film transistorsubstrate and a fabricating method thereof that is adaptive forsimplifying the fabrication process. Also, the present invention isdirected to a liquid crystal display panel employing the thin filmtransistor substrate and a fabricating method thereof that is adaptivefor simplifying the fabrication process.

2. Description of the Related Art

Generally, a liquid crystal display (LCD) controls the lighttransmittance of a liquid crystal having a dielectric anisotropy usingan electric field to thereby display a picture. To this end, the LCDincludes a liquid crystal display panel for displaying a picture using aliquid crystal cell matrix and a driving circuit to drive the liquidcrystal display panel.

Referring to FIG. 1, a related art liquid crystal display panel includesa color filter substrate 10 and a thin film transistor substrate 20 thatare joined to each other having a liquid crystal 24 therebetween.

The color filter substrate 10 includes a black matrix 4, a color filter6 and a common electrode 8 that are sequentially provided on an upperglass substrate 2. The black matrix 4 is provided in a matrix on theupper glass substrate 2. The black matrix 4 divides an area of the upperglass substrate 2 into a plurality of cell areas containing the colorfilters 6 and prevents light interference between adjacent cells andexternal light reflections. The color filters 6 are placed in the cellarea defined by the black matrix 4, with adjacent cells alternatingbetween red(R), green(G) and blue(B) filters, thereby transmitting red,green and blue light. The common electrode 8 is formed from atransparent conductive layer entirely coated onto the color filter 6,and supplies a common voltage Vcom that serves as a reference voltagefor driving of the liquid crystal 24. Further, an over-coat layer (notshown) to smooth the color filter 6 may be provided between the colorfilter 6 and the common electrode 8.

The thin film transistor substrate 20 includes a thin film transistor 18and a pixel electrode 22 provided for each cell defined by a gate line14 crossing a data line 16 on a lower glass substrate 12. The thin filmtransistor 18 applies a data signal from the data line 16 to the pixelelectrode 22 in response to a gate signal from the gate line 14. Thepixel electrode 22 formed from a transparent conductive layer supplies adata signal from the thin film transistor 18 to drive the liquid crystal24.

The liquid crystal 24 having a dielectric anisotropy is rotated by anelectric field formed by a data signal on the pixel electrode 22 and acommon voltage Vcom on the common electrode 8 to control the lighttransmittance of the liquid crystal 24, thereby implementing a grayscale level.

Further, the liquid crystal display panel may include a spacer (notshown) to fix a cell gap between the color filter substrate 10 and thethin film transistor substrate 20.

In the liquid crystal display panel, the color filter substrate 10, andthe thin film transistor substrate 20 are formed by a plurality of maskprocesses. One mask process includes a number of processes such as thinfilm deposition (coating), cleaning, photolithography, etching,photo-resist stripping and inspection processes, etc.

Because the fabrication of the thin film transistor substrate includessemiconductor fabricated processes and requires a plurality of maskprocesses, the manufacturing cost the liquid crystal display panelincreases because of the complexity of the manufacturing processes.Therefore, the thin film transistor substrate of the present inventionhas been developed to reduce the number of mask processes.

SUMMARY OF THE INVENTION

Accordingly, the present invention is directed to a liquid crystaldisplay device and fabricating method thereof that substantiallyobviates one or more of the problems due to limitations anddisadvantages of the related art.

An advantage of the present invention is to provide a thin filmtransistor substrate and a fabricating method thereof and a liquidcrystal display panel employing the same and a fabricating methodthereof that simplify the manufacturing process.

Additional features and advantages of the invention will be set forth inthe description which follows, and in part will be apparent from thedescription, or may be learned by practice of the invention. Theobjectives and other advantages of the invention will be realized andattained by the structure particularly pointed out in the writtendescription and claims hereof as well as the appended drawings.

To achieve these and other advantages and in accordance with the purposeof the present invention, as embodied and broadly described, a liquidcrystal display device, including: first and second substrates; a gateline on the first substrate; a data line crossing the gate line having agate insulating film therebetween to define a pixel area; a pixelelectrode formed of a transparent conductive film in a pixel holepassing through the gate insulating film in the pixel area; and a thinfilm transistor including a gate electrode, a source electrode, a drainelectrode, and a semiconductor layer defining a channel between thesource electrode and the drain electrode, wherein the semiconductorlayer overlaps with a source and rain metal pattern including the dataline, the source electrode and the drain electrode; and wherein thedrain electrode protrudes from the semiconductor layer toward inside ofthe pixel electrode to be connected to the pixel electrode.

In another aspect of the present invention, a method of fabricating aliquid crystal display device, including: a first mask process offorming a gate line and a gate electrode connected to the gate line onthe first substrate; a second mask process including forming a gateinsulating film on the gate line and the gate electrode and forming asemiconductor layer, then defining a pixel hole that passes through thegate insulating film and the semiconductor layer in a pixel area, andforming a pixel electrode in the pixel hole; and a third mask processincluding forming a source and drain metal pattern having a data linecrossing the gate line to define the pixel area, a source electrode anda drain electrode on the first substrate, and exposing an active layerof the semiconductor pattern to define a channel between the sourceelectrode and the drain electrode.

It is to be understood that both the foregoing general description andthe following detailed description are exemplary and explanatory and areintended to provide further explanation of the invention as claimed.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are included to provide a furtherunderstanding of the invention and are incorporated in and constitute apart of this specification, illustrate embodiments of the invention andtogether with the description serve to explain the principles of theinvention.

In the drawings:

FIG. 1 is a schematic perspective view showing a structure of a relatedart liquid crystal display panel;

FIG. 2 is a plan view showing a portion of a thin film transistorsubstrate according to a first embodiment of the present invention;

FIG. 3 is a section view of the thin film transistor substrate takenalong the II-II′, III-III′ and IV-IV′ lines in FIG. 2;

FIG. 4 is a section view showing a data pad area of a liquid crystaldisplay panel employing the thin film transistor substrate shown in FIG.3;

FIG. 5A and FIG. 5B are a plan view and a section view showing a firstmask process in a method of fabricating the thin film transistorsubstrate according to the embodiment of the present invention,respectively;

FIG. 6A and FIG. 6B are a plan view and a section view showing a secondmask process in a method of fabricating the thin film transistorsubstrate according to the embodiment of the present invention,respectively;

FIG. 7A to FIG. 7C are section views for specifically explaining thesecond mask process;

FIG. 8A and FIG. 8B are a plan view and a section view showing a thirdmask process in a method of fabricating the thin film transistorsubstrate according to the embodiment of the present invention,respectively;

FIG. 9A to FIG. 9D are section views for specifically explaining thethird mask process;

FIG. 10 is a plan view showing a portion of a thin film transistorsubstrate according to a second embodiment of the present invention;

FIG. 11 is a section view of the thin film transistor substrate takenalong the II-II′, III-III′ and IV-IV′ lines in FIG. 10;

FIG. 12 is a plan view showing a portion of a thin film transistorsubstrate according to a third embodiment of the present invention;

FIG. 13 is a section view of the thin film transistor substrate takenalong the II-II′, III-III′ and IV-IV′ lines in FIG. 12;

FIG. 14 is a plan view showing a portion of a thin film transistorsubstrate according to a fourth embodiment of the present invention;

FIG. 15 is a section view of the thin film transistor substrate takenalong the II-II′, III-III′ and IV-IV′ lines in FIG. 14;

FIG. 16A and FIG. 16B are section views for explaining a method offabricating a protective film according to another embodiment of thepresent invention; and

FIG. 17A and FIG. 17B are section views for explaining a fabricatingmethod of the protective film in a method of fabricating the liquidcrystal display panel employing the thin film transistor substrateaccording to the embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

Reference will now be made in detail to an embodiment of the presentinvention, example of which is illustrated in the accompanying drawings.

Hereinafter, the preferred embodiments of the present invention will bedescribed in detail with reference to FIGS. 2 to 17B.

FIG. 2 is a plan view showing a portion of a thin film transistorsubstrate according to a first embodiment of the present invention, andFIG. 3A and FIG. 3B are section views of the thin film transistorsubstrate taken along the II-II′, III-III′ and IV-IV′ lines in FIG. 2.

Referring to FIG. 2 and FIG. 3, the thin film transistor substrateincludes a gate line 102 and a data line 104 on a lower substrate 142 insuch a manner to cross each other with a gate insulating film 144therebetween, a thin film transistor 106 connected to the gate line 102and the data line 104 near each crossing, and a pixel electrode 118 in apixel area defined by the crossing structure. Further, the thin filmtransistor substrate includes a storage capacitor 120 provided at anoverlapped portion between the pixel electrode 118 and the gate line102, a gate pad 126 connected to the gate line 102, and a data pad 134connected to the data line 104.

The thin film transistor 106 allows a pixel signal applied to the dataline 104 to be charged onto the pixel electrode 118 and stored inresponse to a scanning signal applied to the gate line 102. To this end,the thin film transistor 106 includes a gate electrode 108 connected tothe gate line 102, a source electrode 110 connected to the data line104, a drain electrode 112 positioned in opposition to the sourceelectrode 110 to be connected to the pixel electrode 118, an activelayer 114 overlapping with the gate electrode 108 with having the gateinsulating film 144 therebetween to provide a channel between the sourceelectrode 110 and the drain electrode 112, and an ohmic contact layer116 formed on the active layer 114 except in the channel region to makean ohmic contact with the source electrode 110 and the drain electrode112.

Further, a semiconductor layer 115 including the active layer 114 andthe ohmic contact layer 116 overlaps the data line 104.

A pixel hole 170 passes through the gate insulating film 144 in a pixelarea defined by the crossing of the gate line 102 and the data line 104.The pixel electrode 118 interfaces with the edge of the gate insulatingfilm 144 within the pixel hole 170 and is on the substrate 142 to beexposed. Thus, the pixel electrode 118 is connected to the drainelectrode 112 that protrudes from the thin film transistor 196 towardthe inside of the pixel hole 170. The pixel electrode 118 stores a pixelsignal supplied from the thin film transistor 106 as a charge togenerate a potential difference with respect to a common electrode on acolor filter substrate (not shown). This potential difference rotates aliquid crystal positioned between the thin film transistor substrate andthe color filter substrate due to a dielectric anisotropy and controlsthe amount of a light from a light source (not shown) passing throughthe liquid crystal, electrode 118, and the color filter substrate.

The storage capacitor 120 is formed such that an upper storage electrode122 connected to the pixel electrode 118 overlaps with a portion of thepre-stage gate line 102 having the gate insulating film 144therebetween. The upper storage electrode 122 overlaps with a portion ofthe pre-stage gate line 102 and protrudes toward the inside of the pixelhole 170 to be connected to the pixel electrode 118. The semiconductorlayer 115 with the active layer 114 and the ohmic contact layer 116further overlaps the upper storage electrode 122 and the gate insulatingfilm 144. The storage capacitor 120 allows a pixel signal charged on thepixel electrode 118 to be stably maintained.

The gate line 102 receives a scanning signal from a gate driver via thegate pad 126. The gate pad 126 consists of a lower gate pad electrode128 extended from the gate line 102, and an upper gate pad electrode 132provided within a first contact hole 130 passing through the gateinsulating film 144 to connect to the lower gate pad electrode 128. Theupper gate pad electrode 132, along with the pixel electrode 118, isformed from a transparent conductive layer, and makes an interface withthe edge of the gate insulating film 144 enclosing the first contacthole 130.

The data line 104 receives a pixel signal from a data driver via a datapad 134. The data pad 134 is formed from a transparent conductive layerwithin a second contact hole 138 passing through the gate insulatingfilm 144 along with the upper gate pad electrode 132. The second contacthole 138 of the data pad 134 extends to overlap with a portion of thedata line 104. Thus, the data line 104 protrudes from the semiconductorlayer 115 toward the inside of the second contact hole 138, so that itconnects to the extended portion of the data pad 134.

In this case, the data line 104 is exposed due to an absence of theprotective film. In order to prevent the data line 104 from beingexposed and oxidized, as shown in FIG. 4, the extended portion of thedata pad 134 and the connecting portion of the data line 104 arepositioned within an area sealed by a sealant 320. The data line 104 inthe sealed area is coated with a lower alignment film 312, therebyprotecting the data line 104 from oxidation thereon.

Referring to FIG. 4, a thin film transistor substrate coated with thelower alignment film 312 and a color filter substrate 300 coated with anupper alignment film 310 are joined to each other by the sealant 320,and a cell gap between two substrates sealed by the sealant 320 isformed with a liquid crystal. The upper and lower alignment films 310and 312 are coated with an organic insulating material in a picturedisplay area of the two substrates. The sealant 320 is placed so as tonot be in contact with the upper and lower alignment films 310 and 312so as to have better adhesion to the two substrates. Thus, the data line104 provided at the thin film transistor substrate, along with thesource electrode 110 and the drain electrode 112, is positioned in anarea sealed by the sealant 320, so that it can be sufficiently protectedby the lower alignment film 312 as well as by the liquid crystal formedin the sealed area.

As described above, in the thin film transistor substrate according tothe first embodiment of the present invention, a transparent conductivepattern including the pixel electrode 118, the upper gate pad electrode132 and the data pad 140 is formed by an etching process using aphoto-resist pattern to define the pixel hole 170 passing through thegate insulating film 144 and the contact holes 130 and 138. Thus, thetransparent conductive pattern is provided on the substrate 142 in orderto make an interface with the edge of the gate insulating film 144enclosing the corresponding hole.

Further, the semiconductor layer 115 is formed like the gate insulatingfilm 144 and then has an exposed portion removed upon formation of asource/drain metal pattern including the data line 104, the sourceelectrode 110, the drain electrode 112, and the upper storage electrode122. Further, upon formation of the source/drain metal pattern, theactive layer 114 is exposed to define a channel of the thin filmtransistor 106. Thus, the semiconductor layer 115 has a channel formedonly at the channel portion between the source electrode 110 and thedrain electrode 112 and the overlapping portion between the source/drainmetal pattern and the gate insulating film 144. A surface layer 124 ofthe exposed active layer 114 is surface treated by plasma, so that theactive layer 114 of the channel may be protected by the surface layer124 oxidized by SiO₂.

The thin film transistor substrate according to the first embodiment ofthe present invention having the above-mentioned structure may be formedby the following three-round mask process.

FIG. 5A and FIG. 5B are a plan view and a section view, respectively,for explaining a first mask process in a method of fabricating the thinfilm transistor substrate according to an embodiment of the presentinvention.

A gate metal pattern including the gate line 102, the gate electrode 108connected to the gate line 102, and the lower gate pad electrode 128 isformed on the lower substrate 142 by the first mask process.

More specifically, a gate metal layer is formed on the lower substrate142 by a deposition technique such as the sputtering, etc. The gatemetal layer employs a single layer formed of a metal material such asMo, Ti, Cu, AlNd, Al, Cr, a Mo alloy, a Cu alloy or an Al alloy, etc.,or takes a stacked structure of at least double layers such as Al/Cr,Al/Mo, Al(Nd)/Al, Al(Nd)/Cr, Mo/Al(Nd)/Mo, Cu/Mo, Ti/Al(Nd)/Ti, Mo/Al,Mo/Ti/Al(Nd), Cu-alloy/Mo, Cu-alloy/Al, Cu-alloy/Mo-alloy,Cu-alloy/Al-alloy, Al/Mo alloy, Mo-alloy/Al, Al-alloy/Mo-alloy,Mo-alloy/Al-alloy, Mo/Al alloy, Cu/Mo alloy or Cu/Mo(Ti), etc. Then, thegate metal layer is patterned by photolithography and an etching processusing a first mask to thereby produce the gate metal pattern includingthe gate line 102, the gate electrode 108, and the lower gate padelectrode 128.

FIG. 6A and FIG. 6B are a plan view and a section view, respectively,for explaining a second mask process in a method of fabricating the thinfilm transistor substrate according to the embodiment of the presentinvention and FIG. 7A to FIG. 7C are section views for specificallyexplaining the second mask process.

The gate insulating film 144, the active layer 114, and the ohmiccontact layer 116 are disposed on the lower substrate 142 including thegate metal pattern. The pixel hole 170 and the first and second contactholes 130 and 138 passing through the gate insulating film 144 aredefined by the second mask process. Further, a transparent conductivepattern including the pixel electrode 118, the upper gate pad electrode132, and the data pad 134 is formed within the corresponding hole.

Referring to FIG. 7A, the gate insulating film 144 and the semiconductorlayer 115 including the active layer 114 and the ohmic contact layer 116are sequentially disposed on the lower substrate 142 including the gatemetal pattern by a deposition technique such as the PECVD, etc. Herein,the gate insulating film 144 is formed from an inorganic insulatingmaterial such as silicon nitride (SiN_(x)) or silicon oxide (SiO_(x)),whereas the active layer 114 and the ohmic contact layer 116 are formedfrom an amorphous silicon or an amorphous silicon doped with an n⁺ or p⁺impurity.

Subsequently, a first photo-resist pattern 200 is formed on the ohmiccontact layer 116 by photolithography using a second mask, and the pixelhole 170 and the first and second contact holes 130 and 138 are formedby the etching process using the first photo-resist pattern 200 as amask. The pixel hole 170 and the first and second contact holes 130 and138 pass through an area extending from the ohimc contact layer 116 tothe gate insulating film 144. The semiconductor layer 115 and the gateinsulating film 144 are over-etched such that the edges of the pixelhole 170 and the first and second contact holes 130 and 138 arepositioned inside and under the edge of the first photo-resist pattern200, thereby under-cutting the first photo-resist pattern 200. The pixelhole 170 and the second contact hole 138 expose the substrate 142,whereas the first contact hole 130 exposes the lower gate pad electrode128 and the substrate 142 at the edge of the electrode 128.

Referring to FIG. 7B, the transparent conductive layer 117 is entirelyformed on the substrate 142 provided with the first photo-resist pattern200 by a deposition technique such as sputtering, etc. The transparentconductive layer 117 is formed of ITO, TO, IZO or ITZO, etc. Thus, thepixel electrode 118 is formed within the pixel hole 170; the upper gatepad electrode 132 is formed within the first contact hole 130; and thedata pad 134 is formed within the second contact hole 138. Thistransparent conductive pattern leaves an opening at the edge of thefirst photo-resist pattern 200 near the edges of the pixel hole 170 andthe first and second contact holes 130 and 138. Further, the transparentconductive pattern is formed along the edges of the pixel hole 170 andthe first and second contact holes 130 and 138 to interface with thegate insulating film 144 enclosing the corresponding hole. Accordingly,stripper infiltration between the first photo-resist pattern 200 and theohmic contact layer 116 is facilitated during the lift-off process ofremoving the first photo-resist pattern 200 coated with the transparentconductive film 117, thereby improving lift-off efficiency.

Referring to FIG. 7C, the first photo-resist pattern 200 coated with thetransparent conductive film 117 shown in FIG. 7B is removed by thelift-off process.

FIG. 8A and FIG. 8B are a plan view and a section view, respectively,for explaining a third mask process in a method of fabricating the thinfilm transistor-substrate according to an embodiment of the presentinvention and FIG. 9A to FIG. 9D are section views for specificallyexplaining the third mask process.

A source/drain metal pattern including the data line 104, the sourceelectrode 110, the drain electrode 112 and the storage electrode 122 isformed on the lower substrate 142 having a semiconductor layer 115 andthe transparent conductive pattern by the three mask process. Further,the semiconductor layer 115 not overlapping with the source/drain metalpattern is removed, and the active layer 114 between the sourceelectrode 110 and the drain electrode 112 is also exposed, therebydefining a channel of the thin film transistor 106. The source/drainmetal pattern and the channel of the thin film transistor 106 are formedby a single mask process employing a partial transmitting mask such as adiffractive exposure mask or a half tone mask, etc.

Referring to FIG. 9A, a source/drain metal layer is formed on the lowersubstrate 142 that includes the semiconductor layer 115 and thetransparent conductive pattern by a deposition technique such as thesputtering, etc. The source/drain metal layer employs a single layerformed of a metal material such as Mo, Ti, Cu, AlNd, Al, Cr, a Mo alloy,a Cu alloy or an Al alloy, etc., or takes a stacked structure of atleast double layers such as Al/Cr, Al/Mo, Al(Nd)/Al, Al(Nd)/Cr,Mo/Al(Nd)/Mo, Cu/Mo, Ti/Al(Nd)/Ti, Mo/Al, Mo/Ti/Al(Nd), Cu-alloy/Mo,Cu-alloy/Al, Cu-alloy/Mo-alloy, Cu-alloy/Al-alloy, Al/Mo alloy,Mo-alloy/Al, Al-alloy/Mo-alloy, Mo-alloy/Al-alloy, Mo/Al alloy, Cu/Moalloy or Cu/Mo(Ti), etc.

Subsequently, a second photo-resist pattern 210 including photo-resistpatterns 210A and 210B having a different thickness is formed on thesource/drain metal layer by photolithography using a partialtransmitting mask. The partial transmitting mask includes a shieldingportion that shields the ultraviolet rays, a partial transmittingportion that diffracts the ultraviolet rays using a slit pattern or thatpartially transmits the ultraviolet ray using a phase-shifting material,and a full transmitting portion that fully transmits the ultravioletrays. The second photo-resist pattern 210 including different thicknessphoto-resist patterns 210A and 210B and an aperture portion is formed byusing photolithography with the partial transmitting mask. In this case,a relatively thick photo-resist pattern 210A is provided at a shieldingarea P1 overlapping the shielding part of the partial transmitting mask;the photo-resist pattern 210B that is thinner than the photo-resistpattern 210A is provided at a partial exposure area P2 overlapping thepartial transmitting portion; and the aperture portion is provided at anfull exposure area P3 overlapping the full transmitting portion.

Further, the source/drain metal layer is patterned by an etching processusing the second photo-resist pattern 210 to thereby provide thesource/drain metal pattern including the data line 104, the drainelectrode 112, and the source electrode 110 and the storage electrode122. The source/drain metal layer is patterned by a wet etching process,so that the source/drain metal pattern has an over-etched structure incomparison to the second photo-resist pattern 210. The drain electrode112 and the lower storage electrode 122 protrudes from the overlappingportion the semiconductor layer 115 and the gate insulating film 144toward the inside of the pixel hole 170 to be connected to the pixelelectrode 118. Herein, the lower storage electrode 122 overlaps with aportion of the pre-stage gate line 102 with having the semiconductorlayer 115 and the gate insulating film 144 therebetween, therebyproviding the storage capacitor 120. The data line 104 also protrudesfrom the overlapping portion of the semiconductor layer 115 and the gateinsulating film 144 into the second contact hole 138 to be connected tothe data pad 134.

Referring to FIG. 9B, the semiconductor layer 115 exposed by the secondphoto-resist pattern 210 is etched, so that the semiconductor layer 115exists only in the area where it overlaps the second photo-resistpattern 210. The exposed semiconductor layer 115 is etched by a dryetching process by utilizing the second photo-resist pattern 210 as amask. Thus, the semiconductor layer 115 remains in the area where itoverlaps the second photo-resist pattern 210 used to form thesource/drain metal pattern, and as a result it overlaps the source/drainmetal pattern. Also, the edge of the semiconductor layer 115 protrudesfrom under the source/drain metal pattern. As a result, the source/drainmetal pattern covers the semiconductor layer 115 with a step shape.

Referring to FIG. 9C, the thickness of the photo-resist pattern 210A isthinned, and the photo-resist pattern 210B is removed by the ashingprocess using an oxygen (O2) plasma. Such an ashing process may beincorporated with the dry etching process for etching the exposedsemiconductor layer 115 and performed within the same chamber. Further,the exposed source/drain metal pattern and the ohmic contact layer 116are removed by the etching process using the ashed photo-resist pattern210A. Thus, the source electrode 110 and the drain electrode 112 aredisconnected from each other, and the thin film transistor 106 having achannel with the exposed active layer 114 between the electrodes iscompleted.

Furthermore, the surface of the active layer 114 exposed by the surfacetreatment process using an oxygen (O2) plasma is oxidized by SiO2. Thus,the active layer 114 defining channel of the thin film transistor 106may be protected by the surface layer 124 oxidized by SiO2.

Referring to FIG. 9D, the photo-resist pattern 210A shown in FIG. 9C isremoved by a stripping process.

As described above, the method of fabricating the thin film transistorsubstrate according to the first embodiment of the present invention mayreduce the number of processes with the three step mask process.

FIG. 10 is a plan view showing a portion of a thin film transistorsubstrate according to a second embodiment of the present invention, andFIG. 11 is a section view of the thin film transistor substrate takenalong the II-II′, III-III′ and IV-IV′ lines in FIG. 10.

The thin film transistor substrate shown in FIG. 10 and FIG. 11 has thesame elements as the thin film transistor substrate shown in FIG. 2 andFIG. 3 except that a data pad 234 has a vertical structure identical tothe gate pad 126; and it further includes a contact electrode 252 toconnect a data link 250 extending from the data pad 234 to the data line104. Therefore, an explanation as to the same elements as found in FIG.2 and FIG. 3A will be omitted.

Referring to FIG. 10 and FIG. 11, the data pad 234 includes a lower datapad electrode 236 provided on the substrate 142 and an upper data padelectrode 240 provided within a second contact hole 238 passing throughthe gate insulating film 144 to expose the lower data pad electrode 236and connected to the lower data pad electrode 236 similar to the gatepad 126.

The data link 250 extends from the lower electrode 236 of the data pad234 so as to overlap with the data line 104 and is exposed through athird contact hole 254 passing through the gate insulating film 144. Thedata link 250 is connected, via the contact electrode 252 in the thirdcontact hole 254, to the data line 104.

The lower data pad electrode 236 and the data link 250, along with thelower gate pad electrode 128, are created by the first mask process. Thesecond and third contact holes 238 and 254, along with the first contacthole 130, are formed by the second mask process. In the second maskprocess, the upper data pad electrode 240 and the contact electrode 252,along with the upper gate pad electrode 132, are formed within thesecond and third contact holes 238 and 254, respectively. In this case,the upper data pad electrode 240 and the contact electrode 252 interfacewith the edge of the gate insulating film 144 and enclose the second andthird contact holes 238 and 254.

Further, the data line 104 is positioned within an area sealed by thesealant, so that it can be protected by the alignment film coatedthereon or the liquid crystal formed in the sealed area. To this end,the contact electrode 252 that connects the data line 104 to the datalink 250 is located within the sealed area.

FIG. 12 is a plan view showing a portion of a thin film transistorsubstrate according to a third embodiment of the present invention, andFIG. 13 is a section view of the thin film transistor substrate takenalong the II-II′, III-III′ and IV-IV′ lines in FIG. 12.

The thin film transistor substrate shown in FIG. 12 and FIG. 13 has thesame elements as the thin film transistor substrate shown in FIG. 10 andFIG. 11 except that an upper data pad electrode 240 and a contact hole252 are integrally formed within a second contact hole 238 extendedalong a data link 250. Therefore, an explanation as to the same elementsas found in FIG. 10 and FIG. 11 will be omitted.

Referring to FIG. 12 and FIG. 13, the second contact hole 238 of thedata pad 234 extends along the data link 250 in such a manner to overlapwith the data line 104. Thus, the upper data pad electrode 240 and thecontact electrode 252 are formed in an integral structure within thesecond contact hole 238 to be connected to the data line 104. The upperdata pad electrode 240 and the contact electrode 252 interface with theedge of the gate insulating film 144 enclosing the second contact hole238.

FIG. 14 is a plan view showing a portion of a thin film transistorsubstrate according to a fourth embodiment of the present invention, andFIG. 15 is a section view of the thin film transistor substrate takenalong the II-II′, III-III′ and IV-IV′ lines in FIG. 14.

The thin film transistor substrate shown in FIG. 14 and FIG. 15 has thesame elements as the thin film transistor substrate shown in FIG. 12 andFIG. 13 except that it further includes a protective film 150 that isplaced outside the gate pad area 126 and the data pad area 234.Therefore, an explanation as to the same elements as found in FIG. 14and FIG. 15 will be omitted.

Referring to FIG. 14 and FIG. 15, the protective film 150 is formed onthe substrate 142 with the source/drain metal pattern so as to be openat the pad area where the gate pad 126 and the data pad 134 areprovided. The protective film 150 may be formed from an inorganicinsulating film like the gate insulating film 144. Alternatively, theprotective film 150 may be formed from an acrylic organic compound, BCB(benzocyclobutene) or PFCB (perfluorocyclobutane), etc.

The protective film 150 is formed by a fourth mask process or by arubber stamp printing system like the alignment film that will be formedinto the uppermost layer. Further, the protective film 150 is entirelyformed on the substrate 142 and then is removed at the pad area by theetching process using the alignment film as a mask or by the etchingprocess using the color filter substrate as a mask after the substrate142 is joined to the color filter substrate.

First, when the fourth mask process is used, the protective film 150 isentirely formed on the substrate 142 provided with the source/drainmetal pattern. In this case, the protective film 150 is formed by PECVD,spin coating or spinless coating, etc. Further, the protective film 150is patterned by photolithography and an etching process using a fourthmask.

Second, the protective film 150 may be printed only at the array areaoutside the pad area by the rubber stamp printing technique that is amethod to form the alignment film to be provided thereon. In otherwords, the protective film 150 is formed by aligning a rubber mask onthe substrate 142 provided with the source/drain metal pattern and thenprinting an insulating material only at an array area outside the padarea by the rubber stamp printing technique.

Third, the protective film 150 is removed at the pad area by an etchingprocess using the alignment film provided thereon. More specifically, asshown in FIG. 16A, the protective film 150 is formed on the entiresubstrate 142, and the alignment film 152 is formed on the protectivefilm 150 using the rubber stamp printing method. Subsequently, as shownin FIG. 16B, the protective film 150 is removed at the pad area by theetching process using the alignment film 152 as a mask.

Fourth, the protective film 150 is removed at the pad area by theetching process using the color filter substrate as a mask. Morespecifically, as shown in FIG. 17A, the thin film transistor substrateprovided with the protective film 150 and having the lower alignmentfilm 312 provided thereon is joined by the sealant 320 to the colorfilter substrate 300 with an upper alignment film 310. Next, as shown inFIG. 17B, the protective film 150 is removed at the pad area by theetching process using the color filter substrate 300 as a mask. In thiscase, the protective film 150 is removed at the pad area by the etchingprocess using plasma or is removed at the pad area by dipping the liquidcrystal display panel in which the thin film transistor substrate isjoined to the color filter substrate 300 into an etching vessel filledwith an etchant.

As described above, according to the present invention, thesemiconductor layer and the gate insulating film are simultaneouslypatterned by a single mask process using the partial transmitting maskto provide a plurality of holes having different depths and to providethe transparent conductive patterns within the plurality of holes by thelift-off process of the photo-resist pattern used in the mask process.

Furthermore, according to the present invention, the semiconductor layerpatterned simultaneously with the gate insulating film is againpatterned upon formation of the source/drain metal pattern to remove theexposed portion thereof, and the active layer between the sourceelectrode and the drain electrode is exposed to define the channel ofthe thin film transistor. Thus, the semiconductor layer exists only inthe channel of the thin film transistor and the overlapping portion ofthe source/drain metal pattern and the gate insulating film.

Moreover, according to the present invention, the protective film has anopen pad area that is provided by the printing technique, the fourthmask process, the etching process using the alignment film as a mask orthe etching process using the color filter substrate as a mask, etc.

Accordingly, the method of fabricating the thin film transistoraccording to the present invention may be simplified by the four stepmask process, so that the material cost, the equipment investment cost,etc. are reduced as well as to improve productivity.

It will be apparent to those skilled in the art that variousmodifications and variation can be made in the present invention withoutdeparting from the spirit or scope of the invention. Thus, it isintended that the present invention cover the modifications andvariations of this invention provided they come within the scope of theappended claims and their equivalents.

1. A liquid crystal display device, comprising: first and secondsubstrates; a gate line on the first substrate; a data line crossing thegate line having a gate insulating film therebetween to define a pixelarea; a pixel electrode formed of a transparent conductive film in apixel hole passing through the gate insulating film in the pixel area;and a thin film transistor including a gate electrode, a sourceelectrode, a drain electrode, and a semiconductor layer defining achannel between the source electrode and the drain electrode, whereinthe semiconductor layer overlaps with a source and drain metal patternincluding the data line, the source electrode and the drain electrode;and wherein the drain electrode protrudes from the semiconductor layertoward inside of the pixel electrode to be connected to the pixelelectrode.
 2. The liquid crystal display device as claimed in claim 1,further comprising a storage electrode connected to the pixel electrode,wherein the storage electrode overlaps with the gate line having thegate insulating film to form a storage capacitor.
 3. The liquid crystaldisplay device as claimed in claim 2, wherein: the semiconductor furtheroverlaps the storage electrode and the gate insulating film; and thestorage electrode protrudes from where it overlaps the semiconductorlayer toward the pixel hole to connect to the pixel electrode.
 4. Theliquid crystal display device as claimed in claim 3, wherein the drainelectrode and the storage electrode are connected to each other abovethe pixel electrode.
 5. The liquid crystal display device as claimed inclaim 1, further comprising: a pad connected to at least one of the gateline and the data line, wherein the pad includes: a lower pad electrodeon the first substrate; a contact hole passing through the gateinsulating film to expose the lower pad electrode; and an upper padelectrode in the contact hole connected to the lower pad electrode. 6.The liquid crystal display device as claimed in claim 5, wherein thelower pad electrode connects to the gate line.
 7. The liquid crystaldisplay device as claimed in claim 5, further comprising: a data linkextending from the lower pad electrode to overlap with the data line;and a contact electrode in a second contact hole passing through thegate insulating film to expose the data link, thereby connecting thedata link to the data line.
 8. The liquid crystal display device asclaimed in claim 7, wherein the contact hole with the upper padelectrode extends along the data link to be integral to the secondcontact hole, and the upper pad electrode is integral to the contactelectrode.
 9. The liquid crystal display device as claimed in claim 7,wherein the transparent conductive pattern including the pixelelectrode, the upper pad electrode, and the contact electrode borderswith the gate insulating film enclosing the corresponding hole.
 10. Theliquid crystal display device as claimed in claim 7, wherein an areawhere the data line contacts the contact electrode is within an area tobe sealed by a sealant upon joining of the first substrate with thesecond substrate.
 11. The liquid crystal display device as claimed inclaim 8, wherein an area where the data line contacts the contactelectrode is within an area to be sealed by a sealant upon joining ofthe first substrate with the second substrate.
 12. The liquid crystaldisplay device as claimed in claim 1, further comprising: a data pad tobe connected to the data line in a contact hole passing through the gateinsulating film, wherein the data pad borders with the gate insulatingfilm enclosing the contact hole.
 13. The liquid crystal display deviceas claimed in claim 12, wherein the data line is within an area to besealed by a sealant upon joining of the first substrate with the secondsubstrate.
 14. The liquid crystal display device as claimed in claim 1,wherein the channel of the thin film transistor includes a surface layeroxidized by a plasma surface treatment.
 15. The liquid crystal displaydevice as claimed in claim 1, wherein the semiconductor layer and thesource and drain metal pattern have a shape.
 16. The liquid crystaldisplay device as claimed in claim 5, further comprising a protectivefilm on the first substrate with an opening at a pad area.
 17. Theliquid crystal display device as claimed in claim 16, further comprisingan alignment film on the protective film.
 18. The liquid crystal displaydevice as claimed in claim 17, wherein the protective film is formedwith the same pattern as the alignment film.
 19. The liquid crystaldisplay device as claimed in claim 12, further comprising a protectivefilm on the first substrate with an opening at a pad area.
 20. Theliquid crystal display device as claimed in claim 19, further comprisingan alignment film on the protective film.
 21. The liquid crystal displaydevice as claimed in claim 20, wherein the protective film is formedwith the same pattern as the alignment film.
 22. The liquid crystaldisplay device as claimed in claim 5, further comprising a protectivefilm on the first substrate, the protective film having the same patternas the second substrate and having an opening at a pad area.
 23. Theliquid crystal display device as claimed in claim 12, further comprisinga protective film on the first substrate, the protective film having thesame pattern as the second substrate and having an opening at a padarea.
 24. The liquid crystal display device as claimed in claim 1,further comprising a liquid crystal layer between the first and secondsubstrates.
 25. A method of fabricating a liquid crystal display device,comprising: providing first and second substrates; a first mask processof forming a gate line and a gate electrode connected to the gate lineon the first substrate; a second mask process including forming a gateinsulating film on the gate line and the gate electrode and forming asemiconductor layer, then defining a pixel hole that passes through thegate insulating film and the semiconductor layer in a pixel area, andforming a pixel electrode in the pixel hole; and a third mask processincluding forming a source and drain metal pattern having a data linecrossing the gate line to define the pixel area, a source electrode anda drain electrode on the first substrate, and exposing an active layerof the semiconductor pattern to define a channel between the sourceelectrode and the drain electrode.
 26. The method as claimed in claim25, wherein the third mask process further includes removing thesemiconductor layer except in the channel and where it overlaps thesource and drain metal pattern and the gate insulating film.
 27. Themethod as claimed in claim 26, wherein the third mask process includes:forming a source and drain metal pattern including a data line and adrain electrode integral to the source electrode on the first substrate;etching a semiconductor layer exposed through the source and drain metalpattern; and exposing the active layer between the source and drainelectrodes to define the channel.
 28. The method as claimed in claim 26,wherein third mask process includes: forming a source and drain metallayer on the first substrate; forming photo-resist patterns having adifferent thicknesses on the source and drain metal layer; patterningthe source and drain metal layer using the photo-resist patterns to formthe source and drain metal pattern including the data line and the drainelectrode being integral to the source electrode; etching asemiconductor layer exposed through the photo-resist patterns; andexposing the active layer between the source and drain electrodesthrough the photo-resist patterns to form the channel.
 29. The method asclaimed in claim 25, wherein the third mask process further includesforming a storage electrode overlapping with the gate line to form astorage capacitor and connected to the pixel electrode.
 30. The methodas claimed in claim 25, wherein: the semiconductor further overlaps thestorage electrode and the gate insulating film; and the drain electrodeand the storage electrode protrude from where they overlap thesemiconductor layer toward the pixel hole to connect to the pixelelectrode.
 31. The method as claimed in claim 25, wherein the drainelectrode and the storage electrode are connected to each other abovethe pixel electrode.
 32. The method as claimed in claim 25, wherein: thefirst mask process further includes forming a lower pad electrodeconnected to the gate line; and the second mask process further includesforming a contact hole to expose the lower pad electrode and forming anupper pad electrode connected to the lower pad electrode in the contacthole.
 33. The method as claimed in claim 25, wherein: the first maskprocess further includes forming a data link and a lower pad electrodeto be connected to the data line on the first substrate; and the secondmask process further includes forming first and second contact holes toexpose the lower pad electrode and the data link and forming an upperpad electrode connected to the lower pad electrode and a contactelectrode connected to the data link and the data line in thecorresponding contact hole.
 34. The method as claimed in claim 33,wherein the first contact hole with the upper pad electrode extendsalong the data link to be integral to second contact hole, and the upperpad electrode is integral to the contact electrode.
 35. The method asclaimed in claim 33, wherein at least one of the pixel electrode, theupper pad electrode, and the contact electrode borders with the gateinsulating film enclosing the corresponding hole.
 36. The method asclaimed in claim 33, wherein a contact area between the data line andthe contact electrode is within an area to be sealed by a sealant uponjoining of the first substrate with the second substrate.
 37. The methodas claimed in claim 32, wherein at least one of the pixel electrode, theupper pad electrode, and the contact electrode borders with the gateinsulating film enclosing the corresponding hole.
 38. The method asclaimed in claim 32, wherein a contact area between the data line andthe contact electrode is within an area to be sealed by a sealant uponjoining of the first substrate with the second substrate.
 39. The methodas claimed in claim 25, wherein the second mask process furtherincludes: forming a contact hole passes through the semiconductor layerand the gate insulating film and overlaps with the data line; andforming a pad connected to the data line in the contact hole.
 40. Themethod as claimed in claim 39, wherein the pad borders with the gateinsulating film enclosing the contact hole.
 41. The method as claimed inclaim 39, wherein the data line is within an area to be sealed by asealant upon joining of the first substrate with the second substrate.42. The method as claimed in claim 25, wherein the third mask processfurther includes surface treating of the channel of the thin filmtransistor to oxidize the surface layer.
 43. The method as claimed inclaim 26, wherein the semiconductor layer and the source/drain metalpattern have a shape.
 44. The method as claimed in claim 32, wherein thesecond mask process includes: forming a photo-resist pattern on thesemiconductor layer; forming the pixel hole and the contact hole usingthe photo-resist pattern as a mask; forming a transparent conductivefilm on the photo-resist pattern, and forming the correspondingtransparent conductive pattern in the pixel hole and the contact hole;and removing the photo-resist pattern formed with the transparentconductive film.
 45. The method as claimed in claim 44, wherein thesemiconductor layer and the gate insulating film are over-etched suchthat the edges of the pixel hole and the contact hole are positionedunder the photo-resist pattern.
 46. The method as claimed in claim 33,wherein the second mask process includes: forming a photo-resist patternon the semiconductor layer; forming the pixel hole and the contact holeusing the photo-resist pattern as a mask; forming a transparentconductive film on the photo-resist pattern, and forming thecorresponding transparent conductive pattern in the pixel hole and thecontact hole; and removing the photo-resist pattern formed with thetransparent conductive film.
 47. The method as claimed in claim 46,wherein the semiconductor layer and the gate insulating film areover-etched such that the edges of the pixel hole and the contact holeare positioned under the photo-resist pattern.
 48. The method as claimedin claim 39, wherein the second mask process includes: forming aphoto-resist pattern on the semiconductor layer; forming the pixel holeand the contact hole using the photo-resist pattern as a mask; forming atransparent conductive film on the photo-resist pattern, and forming thecorresponding transparent conductive pattern in the pixel hole and thecontact hole; and removing the photo-resist pattern formed with thetransparent conductive film.
 49. The method as claimed in claim 48,wherein the semiconductor layer and the gate insulating film areover-etched such that the edges of the pixel hole and the contact holeare positioned under the photo-resist pattern.
 50. The method as claimedin claim 32, further comprising a fourth mask process of forming aprotective film on the first substrate and having an opening at a padarea.
 51. The method as claimed in claim 33, further comprising a fourthmask process of forming a protective film on the first substrate andhaving an opening at a pad area.
 52. The method as claimed in claim 39,further comprising a fourth mask process of forming a protective film onthe first substrate and having an opening at a pad area.
 53. The methodas claimed claim 32, further comprising printing the protective film onthe first substrate so as to have an opening at a pad area.
 54. Themethod as claimed claim 33, further comprising printing the protectivefilm on the first substrate so as to have an opening at a pad area. 55.The method as claimed claim 39, further comprising printing theprotective film on the first substrate so as to have an opening at a padarea.
 56. The method as claimed in claim 32, further comprising: formingthe protective film on the first substrate with the source and drainmetal pattern; forming an alignment film on the protective film; andremoving the protective film at a pad area with the pad by an etchingprocess using the alignment film as a mask.
 57. The method as claimed inclaim 33, further comprising: forming the protective film on the firstsubstrate with the source and drain metal pattern; forming an alignmentfilm on the protective film; and removing the protective film at a padarea with the pad by an etching process using the alignment film as amask.
 58. The method as claimed in claim 39, further comprising: formingthe protective film on the first substrate with the source and drainmetal pattern; forming an alignment film on the protective film; andremoving the protective film at a pad area with the pad by an etchingprocess using the alignment film as a mask.
 59. The method as claimed inclaim 32, further comprising: forming the protective film on the firstsubstrate; attaching the first and second substrates using a sealant;and removing the protective film at a pad area with the pad by anetching process using the second substrate as a mask.
 60. The method asclaimed in claim 33, further comprising: forming the protective film onthe first substrate; attaching the first and second substrates using asealant; and removing the protective film at a pad area with the pad byan etching process using the second substrate as a mask.
 61. The methodas claimed in claim 39, further comprising: forming the protective filmon the first substrate; attaching the first and second substrates usinga sealant; and removing the protective film at a pad area with the padby an etching process using the second substrate as a mask.
 62. Themethod as claimed in claim 25, further comprising forming a liquidcrystal layer between the first and second substrates.